module add_last #(
    parameter WIDTH   = 32,
    parameter VEC_LEN = 64
) (
    input  logic             clk,
    input  logic             rst_n,
    input  logic             in_valid,
    output logic             in_ready,
    input  logic [WIDTH-1:0] in_data,
    output logic             out_valid,
    input  logic             out_ready,
    output logic [WIDTH-1:0] out_data,
    output logic             out_last
);
    logic [$clog2(VEC_LEN)-1:0] cntr;
    logic                       handshake_in;
    logic                       handshake_out;

    assign handshake_in  = in_valid && in_ready;
    assign handshake_out = out_valid && out_ready;

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            cntr <= '0;
        end else if (handshake_in) begin
            if (cntr == VEC_LEN - 1) begin
                cntr <= '0;
            end else begin
                cntr <= cntr + 1;
            end
        end
    end

    assign in_ready  = out_ready;
    assign out_valid = in_valid;
    assign out_data  = in_data;
    assign out_last  = (cntr == VEC_LEN - 1);

endmodule
